Verified Tech JournalistAI & Silicon Lead

Dr. Julian Hayes

Silicon Architect & Emerging Technology Contributor. Specializes in neural processing units (NPU), on-device LLMs, and cryptographic enclaves.

Joined: Oct 13, 2026

2 Articles Published

Articles & Coverage by Dr. Julian Hayes

Silicon wafer fabrication under electron microscope illustration

NewsNews

2d ago

Next-Generation Silicon: 2nm Process Nodes and What to Expect in 2026/2027

TSMC, Intel, and Samsung are racing to deploy Gate-All-Around (GAA) nanosheet transistors. Here is how the 2nm transition will reshape performance and battery efficiency.

By Dr. Julian Hayes4 min read

Macro photography of modern semiconductor wafer and microarchitecture

TechnologyExplainer

2d ago

On-Device AI Silicon: How NPUs Are Changing Smartphone Architecture

We analyze the architectural shift toward dedicated neural processing units, examining TOPS metrics, memory bandwidth bottlenecks, and private on-device LLMs.

By Dr. Julian Hayes5 min read